A. Boot program
B. Bootloader
C. Initializer
D. Bootstrap program

A. Sending signals to cpu through bus
B. Executing a special operation called system call
C. Executing a special program called system program
D. Executing a special program called interrupt trigger program

A. Hardware generated interrupt caused by an error
B. Software generated interrupt caused by an error
C. User generated interrupt caused by an error
D. None of the mentioned

A. Information service request
B. Interrupt service request
C. Interrupt service routine
D. Information service routine

A. It is an address that is indexed to an interrupt handler
B. It is a unique device number that is indexed by an address
C. It is a unique identity given to an interrupt
D. None of the mentioned

A. High speed devices(disks and communications network)
B. Low speed devices
C. Utilizing cpu cycles
D. All of the mentioned

A. The cpu uses polling to watch the control bit constantly, looping to see if a device is ready
B. The cpu writes one data byte to the data register and sets a bit in control register to show that a byte is available
C. The cpu receives an interrupt when the device is ready for the next byte
D. The cpu runs a user written code and does accordingly

A. The cpu uses polling to watch the control bit constantly, looping to see if a device is ready
B. The cpu writes one data byte to the data register and sets a bit in control register to show that a byte is available
C. The cpu receives an interrupt when the device is ready for the next byte
D. The cpu runs a user written code and does accordingly

A. The cpu uses polling to watch the control bit constantly, looping to see if a device is ready
B. The cpu writes one data byte to the data register and sets a bit in control register to show that a byte is available
C. The cpu receives an interrupt when the device is ready for the next byte
D. The cpu runs a user written code and does accordingly

A. Bottom layer(0) is the user interface
B. Highest layer(n) is the user interface
C. Bottom layer(n) is the hardware
D. Highest layer(n) is the hardware