Electrical Engineering Mcqs — Test 111
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Question 1
Class _____________ operation gives the maximum distortion?
Question 2
The size of a power transistor is made considerably large to________________?
Question 3
The universal gate is ________________?
Question 4
The inputs of a NAND gate are connected together. The resulting circuit is _______________?
Question 5
In Boolean algebra, the bar sign (-) indicates__________________?
Question 6
Which type of CPLD packaging can provide maximum number of pins on the package due to small size of the pins ?
Question 7
What would happen, if smaller logic modules are utilized for performing logical functions associated with FPGA? A. Propagation delay will increase B. FPGA area will increase C. Wastage of logic modules will not be prevented D. Number of interconnected paths in device will decrease ?
Question 8
Which mechanism allocates the binary value to the states in order to reduce the cost of the combinational circuits ?
Question 9
What is/are the configurable functions of each and every IOBs connected around the FPGA device from the operational point of view ?
Question 10
The NAND gate is AND gate followed by_________________?