System Administrator 2026
Attempt This Past Paper
The ______ register is written by the host to send output.
  • A. Status
  • B. Control
  • C. Data in
  • D. Data out
The CPU hardware has a wire called __________ that the CPU senses after executing every instruction.
  • A. Interrupt request line
  • B. Interrupt bus
  • C. Interrupt receive line
  • D. Interrupt sense line
In general the two interrupt request lines are ____________
  • A. Maskable & non maskable interrupts
  • B. Blocked & non maskable interrupts
  • C. Maskable & blocked interrupts
  • D. None of the mentioned
The _________ are reserved for events such as unrecoverable memory errors.
  • A. Non maskable interrupts
  • B. Blocked interrupts
  • C. Maskable interrupts
  • D. None of the mentioned
In rate monotonic scheduling ____________
  • A. Shorter duration job has higher priority
  • B. Longer duration job has higher priority
  • C. Priority does not depend on the duration of the job
  • D. None of the mentioned
In which scheduling certain amount of CPU time is allocated to each process?
  • A. Earliest deadline first scheduling
  • B. Proportional share scheduling
  • C. Equal share scheduling
  • D. None of the mentioned
The problem of priority inversion can be solved by ____________
  • A. Priority inheritance protocol
  • B. Priority inversion protocol
  • C. Both priority inheritance and inversion protocol
  • D. None of the mentioned
Time duration required for scheduling dispatcher to stop one process and start another is known as ____________
  • A. Process latency
  • B. Dispatch latency
  • C. Execution latency
  • D. Interrupt latency