In paging the user provides only ________ which is partitioned by the hardware into ________ and ______

• A. One address, page number, offset
• B. One offset, page number, address
• C. Page number, offset, address
• D. None of the mentioned

Each entry in a segment table has a ____________

• A. Segment base
• B. Segment peak
• C. Segment value
• D. None of the mentioned

The segment base contains the ____________

• A. Starting logical address of the process
• B. Starting physical address of the segment in memory
• C. Segment length
• D. None of the mentioned

The segment limit contains the ____________

• A. Starting logical address of the process
• B. Starting physical address of the segment in memory
• C. Segment length
• D. None of the mentioned

The offset ‘d’ of the logical address must be ____________

• A. Greater than segment limit
• B. Between 0 and segment limit
• C. Between 0 and the segment number
• D. Greater than the segment number

If the offset is legal ____________

• A. It is used as a physical memory address itself
• B. It is subtracted from the segment base to produce the physical memory address
• C. It is added to the segment base to produce the physical memory address
• D. None of the mentioned

When the entries in the segment tables of two different processes point to the same physical location ____________

• A. The segments are invalid
• B. The processes get blocked
• C. Segments are shared
• D. All of the mentioned

The protection bit is 0/1 based on ____________

• A. Write only
• B. Read only
• C. Read €? write
• D. None of the mentioned

If there are 32 segments, each of size 1Kb, then the logical address should have ____________

• A. 13 bits
• B. 14 bits
• C. 15 bits
• D. 16 bits

Consider a computer with 8 Mbytes of main memory and a 128K cache. The cache block size is 4 K. It uses a direct mapping scheme for cache management. How many different main memory blocks can map onto a given physical cache block?

• A. 2048
• B. 256
• C. 64
• D. 8